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SET 6


  Question 1

Which one of the following is true for a CPU having a single interrupt request line and a single interrupt grant line?

A : Neither vectored interrupt nor multiple interrupting devices are possible.
B : Vectored interrupts are not possible but multiple interrupting devices are possible.
C : Vectored interrupts and multiple interrupting devices are both possible
D : Vectored interrupt is possible but multiple in­terrupting devices are not possible.


  •  
    .

     Correct answer is :B


  •   Question 2

    Normally user programs are prevented from handling I/O directly by I/O instructions in them. For CPUs having explicit I/O instructions, such I/O protection is ensured by having the I/O instructions privileged. In a CPU with memory mapped I/O, there is no explicit I/O instruction. Which one of the following is true for a CPU with memory mapped I/O?

    A : I/O protection is ensured by operating system routine (s)
    B : I/O protection is ensured by a hardware trap
    C : I/O protection is ensured during system configuration
    D : I/O protection is not possible


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     Correct answer is :A

     Solution :
      User applications are not allowed to perform I/O in user mode - All I/O requests are handled through system calls that must be performed in kernel mode.

  •   Question 3

    Consider a three word machine instruction
    ADD A[R0], @ B
    The first operand (destination) "A [R0]" uses indexed addressing mode with R0 as the index register. The second operand (source) "@ B" uses indirect addressing mode. A and B are memory addresses residing at the second and the third words, respectively. The first word of the instruction specifies the opcode, the index register designation and the source and destination addressing modes. During execution of ADD instruction, the two operands are added and stored in the destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is


    A : 3
    B : 4
    C : 5
    D : 6


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     Correct answer is :B

     Solution :
      In Indexed addressing mode, the base address is already in the instruction i.e A and to fetch the index data from R0 no memory access is required because it's a register So to fetch the operand only 1 memory cycle is required. Indirect Addressing mode requires 2 memory cycles only

  •   Question 4

    Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.



    A : (1, c), (2, b), (3, a)
    B : (1, a), (2, c), (3, b)
    C : (1, b), (2, c), (3, a)
    D : (1, a), (2, b), (3, c)


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    .

     Correct answer is :C


  •   Question 5

    Consider a direct mapped cache of size 32 KB with block size 32 bytes. The CPU generates 32 bit addresses. The number of bits needed for cache indexing and the number of tag bits are respectively

    A : 10,17
    B : 10,22
    C : 15,17
    D : 5,17


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    .

     Correct answer is :A


  •   Question 6

    A 5 stage pipelined CPU has the following sequence of stages: What is the number of clock cycles taken to complete the above sequence of instructions starting from the fetch of I1 ?



    A : 8
    B : 10
    C : 12
    D : 15


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     Correct answer is :A


  •   Question 7

    A device with data transfer rate 10 KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be 4 msec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program controlled mode?

    A : 15
    B : 25
    C : 35
    D : 45


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     Correct answer is :B

     Solution :
      In programmed I/O, CPU does continuous polling,
    To transfer 10KB CPU polls for 1 sec = 10^6 micro-sec of processing
    In interrupt mode CPU is interrupted on completion of io ,
    To transfer 10 KB CPU does 4 micro-sec of processing.
    Gain = 10^6 / 4 = 25000
    250000 for 10000 bytes and 25 for 1 bytes.

  •   Question 8

    Consider the following data path of a CPU.The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR The instruction "add R0, R1" has the register transfer interpretation R0 < = R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is.



    A : 2
    B : 3
    C : 4
    D : 5


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     Correct answer is :B

     Solution :
      Minimum number of clock cycles (execution only) = 3
    1) load Y
    2) input R1, add
    3) output to R1

  •   Question 9

    The, ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR and the next one for loading data from the memory bus into the MDR 79. The instruction "call Rn, sub" is a two word instruction. Assuming that PC is incremented during the fetch cycle of the first word of the instruction, its register transfer interpretation is

    Rn < = PC + 1;
    PC < = M[PC];
    The minimum number of CPU clock cycles needed during the execution cycle of this instruction is:




    A : 2
    B : 3
    C : 4
    D : 5


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     Correct answer is :B

     Solution :
      One cycle to increment PC, one cycle to load PC into MAR, one cycle to fetch memory content and load into PC.

  •   Question 10

    A CPU has 24-bit instructions. A program starts at address 300 (in decimal). Which one of the following is a legal program counter (all values in decimal)?

    A : 400
    B : 500
    C : 600
    D : 700


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     Correct answer is :C


  •   Question 11

    A CPU has a five-stage pipeline and runs at 1 GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instructions following a conditional branch until the branch outcome is known. A program executes 109 instructions out of which 20% are conditional branches. If each instruction takes one cycle to complete on average, the total execution time of the program is:

    A : 1.0 s
    B : 1.2 s
    C : 1.4 s
    D : 1.6 s


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     Correct answer is :C

     Solution :
      Cycle penalty = 0.2 * 2 * 109 = 4 * 109
    Clock speed is 1 GHz and each instruction on average takes 1 cycle. Total execution time = (109 / 109) + 4 * (108 / 109) = 1.4 seconds

  •   Question 12

    Consider a new instruction named branch-on-bit-set (mnemonic bbs). The instruction “bbs reg, pos, label” jumps to label if bit in position pos of register operand reg is one. A register is 32 bits wide and the bits are numbered 0 to 31, bit in position 0 being the least significant. Consider the following emulation of this instruction on a processor that does not have bbs implemented.
    temp <- reg & mask
    Branch to label if temp is non-zero.
    The variable temp is a temporary register. For correct emulation, the variable mask must be generated by


    A : mask <- 0 x 1 & pos
    B : mask <- 0 x ffffffff & pos
    C : mask <- pos
    D : mask <- 0 × f


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     Correct answer is :A


  •   Question 13

    Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-byte block size. The second one is of the same size but direct mapped. The size of an address is 32 bits in both cases. A 2-to-1 multiplexer has a latency of 0.6 ns while a kbit comparator has a latency of k/10 ns. The hit latency of the set associative organization is h1 while that of the direct mapped one is h2. The value of h1 is:

    A : 2.4ns
    B : 2.3ns
    C : 1.8ns
    D : 1.7ns


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     Correct answer is :A


  •   Question 14

    Consider two cache organizations: The first one is 32 KB 2-way set associative with 32-byte block size. The second one is of the same size but direct mapped. The size of an address is 32 bits in both cases. A 2-to-1 multiplexer has a latency of 0.6 ns while a kbit comparator has a latency of k/10 ns. The hit latency of the set associative organization is h1 while that of the direct mapped one is h2. The value of h2 is:

    A : 2.4ns
    B : 2.3ns
    C : 1.8ns
    D : 1.7ns


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     Correct answer is :D


  •   Question 15

    A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a twodimensional array of size 512×512 with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2. P1:
    for (i=0; i<512; i++) {
       for (j=0; j<512; j++) {
          x += A[i][j];
       }
    }
    
    

    P2:
    for (i=0; i<512; i++) {
       for (j=0; j<512; j++) {
          x += A[j][i];
       }
    }

    P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2 . The value of M1 is:


    A : 0
    B : 2048
    C : 16384
    D : 262144


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     Correct answer is :C

     Solution :
      [P1] runs the loops in a way that access elements of A in row major order and [P2] accesses elements in column major order. No of cache blocks = CacheSize/BlockSize = 32KB / 128 Byte = 256 No. of array elements in Each Block = BlockSize/ElementSize = 128 Byte / 8 Byte = 16 Total Misses for [P1] = ArraySize * (No. of array elements in Each Block) / (No of cache blocks) = 512 * 512 * 16 / 256 = 16384

  •   Question 16

    A CPU has a 32 KB direct mapped cache with 128-byte block size. Suppose A is a twodimensional array of size 512×512 with elements that occupy 8-bytes each. Consider the following two C code segments, P1 and P2. P1:
    for (i=0; i<512; i++) {
       for (j=0; j<512; j++) {
          x += A[i][j];
       }
    }
    
    

    P2:
    for (i=0; i<512; i++) {
       for (j=0; j<512; j++) {
          x += A[j][i];
       }
    }

    P1 and P2 are executed independently with the same initial state, namely, the array A is not in the cache and i, j, x are in registers. Let the number of cache misses experienced by P1 be M1 and that for P2 be M2 . The value of the ratio M1/M2 is:


    A : 0
    B : 1/16
    C : 1/8
    D : 16


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     Correct answer is :B

     Solution :
      [P2] runs the loops in a way that access elements of A in row major order and [P2] accesses elements in column major order. No of cache blocks = CacheSize/BlockSize = 32KB / 128 Byte = 256 No. of array elements in Each Block = BlockSize/ElementSize = 128 Byte / 8 Byte = 16 Total Misses for [P1] = ArraySize * (No. of array elements in Each Block) / (No of cache blocks) = 512 * 512 * 16 / 256 = 16384 Total Misses for [P2] = Total Number of elements in array (For every element, there would be a mis

  • MY REPORT
    TOTAL = 16
    ANSWERED =
    CORRECT / TOTAL = /16
    POSITIVE SCORE =
    NEGATIVE SCORE =
    FINAL SCORE =