Loading

SET 5


  Question 1

Consider a 4-way set associative cache consisting of 128 lines with a line size of 64 words. The CPU generates a 20-bit address of a word in main memory. The number of bits in the TAG, LINE and WORD fields arerespectively:

A : 9,6,5
B : 7,7,6
C : 7,5,8
D : 9,5,6


  •  
    .

     Correct answer is :C


  •   Question 2

    Consider a disk pack with 16 surfaces, 128 tracks per surface and 256 sectors per track. 512 bytes of data are stored in a bit serial manner in a sector. The capacity of the disk pack and the number of bits required to specify a particular sector in the disk are respectively:

    A : 256 Mbyte, 19 bits
    B : 256 Mbyte, 28 bits
    C : 512 Mbyte, 20 bits
    D : 64 Mbyte, 28 bits


  •  
    .

     Correct answer is :A

     Solution :
      Capacity of the disk = 16 surfaces X 128 tracks X 256 sectors X 512 bytes = 256 Mbytes.
    To calculate number of bits required to access a sector, we need to know total number of sectors. Total number of sectors = 16 surfaces X 128 tracks X 256 sectors = 2^19
    So the number of bits required to access a sector is 19.

  •   Question 3

    Consider a pipelined processor with the following four stages:
    IF: Instruction Fetch
    ID: Instruction Decode and Operand Fetch
    EX: Execute
    WB: Write Back
    The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX stage dependson the instruction. The ADD and SUB instructions need 1 clock cycle and the MUL instruction needs 3 clock cycles in the EX stage. Operand forwarding is used in the pipelined processor. What is the number of clock cycles taken to complete the following sequence of instructions?


    A : 7
    B : 8
    C : 10
    D : 14


  •  
    .

     Correct answer is :B


  •   Question 4

    Consider the following program segment. Here R1, R2 and R3 are the general purpose registers.
    Assume that the content of memory location 3000 is 10 and the content of the register R3 is 2000. The content of each of the memory locations from 2000 to 2010 is 100. The program is loaded from the memory location 1000. All the numbers are in decimal. Assume that the memory is word addressable. The number of memory references for accessing the data in executing the program completely is:




    A : 10
    B : 11
    C : 20
    D : 21


  •  
    .

     Correct answer is :D


  •   Question 5

    Consider the data given in above question. Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is:

    A : 100
    B : 101
    C : 102
    D : 110


  •  
    .

     Correct answer is :A


  •   Question 6

    Consider the data given in above questions. Assume that the memory is byte addressable and the word size is 32 bits. If an interrupt occurs during the execution of the instruction “INC R3”, what return address will be pushed on to the stack?

    A : 1005
    B : 1020
    C : 1024
    D : 1040


  •  
    .

     Correct answer is :C


  •   Question 7

    Consider a machine with a byte addressable main memory of 1016 bytes. Assume that a direct mapped data cache consisting of 32 lines of 64 bytes each is used in the system. A 50 × 50 two-dimensional array of bytes is stored in the main memory starting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice. Assume that the contents of the data cache do not change in between the two accesses. How many data cache misses will occur i

    A : 40
    B : 50
    C : 56
    D : 59


  •  
    .

     Correct answer is :C


  •   Question 8

    Consider a machine with a byte addressable main memory of 1016 bytes. Assume that a direct mapped data cache consisting of 32 lines of 64 bytes each is used in the system. A 50 × 50 two-dimensional array of bytes is stored in the main memory starting from memory location 1100H. Assume that the data cache is initially empty. The complete array is accessed twice. Assume that the contents of the data cache do not change in between the two accesses.Which of the following lines of the data cache will

    A : line 4 to line 11
    B : line 4 to line 12
    C : line 0 to line 7
    D : line 0 to line 8


  •  
    .

     Correct answer is :A


  •   Question 9

    Which of the following is/are true of the auto-increment addressing mode?
    I. It is useful in creating self-relocating code.
    II. If it is included in an Instruction Set Architecture, then an additional ALU is required for effective address calculation.
    III.The amount of increment depends on the size of the data item accessed.


    A : I only
    B : II only
    C : III only
    D : II and III only


  •  
    .

     Correct answer is :C


  •   Question 10

    Which of the following must be true for the RFE (Return from Exception) instruction on a general purpose processor?
    I. It must be a trap instruction
    II. It must be a privileged instruction
    III. An exception cannot be allowed to occur during execution of an RFE instruction


    A : I only
    B : II only
    C : I and II only
    D : I,II and III only


  •  
    .

     Correct answer is :D

     Solution :
      RFE (Return From Exception) is a privileged trap instruction that is executed when exception occurs, so an exception is not allowed to execute. (D) is the correct option.

  •   Question 11

    For inclusion to hold between two cache levels L1 and L2 in a multi-level cache hierarchy, which of the following are necessary?
    I. L1 must be a write-through cache
    II. L2 must be a write-through cache
    III. The associativity of L2 must be greater than that of L1
    IV. The L2 cache must be at least as large as the L1 cache


    A : IV only
    B : I and IV  only
    C : I,III and IV only
    D : I,II,III and IV


  •  
    .

     Correct answer is :A

     Solution :
      L1 and L2 cache are placed between CPV & they can be both write through cache but not necessary. Associativity doesn't matter. L2 cache must be at least as large as L1 cache, since all the words in L1 are also is L2.

  •   Question 12

    Which of the following are NOT true in a pipelined processor?
    I. Bypassing can handle all RAW hazards.
    II. Register renaming can eliminate all register carried WAR hazards.
    III. Control hazard penalties can be eliminated by dynamic branch prediction.


    A : I and II only
    B : I and III only
    C : II and III only
    D : I, II and III


  •  
    .

     Correct answer is :D

     Solution :
      i) In a Pipelined processor bypassing can’t handle all the raw hazards. A read after write (RAW) data hazard refers to a situation where an instruction refers to a result that has not yet been calculated or retrieved. This can occur because even though an instruction is executed after a previous instruction, the previous instruction has not been completely processed through the pipeline.Consider when any instruction depends on the result of LOAD instruction, now LOAD updates register value at Memory Access Stage (MA), so data will not be available directly on Execute stage. ii) WAR(Write After Read ) A write after read (WAR) data hazard represents a problem with concurrent execution. Register carried WAR does not have register renaming as proper solution because If programs refrained from reusing registers immediately, there would be no need for register renaming.

  •   Question 13

    The use of multiple register windows with overlap causes a reduction in the number of memory accesses for
    I. Function locals and parameters
    II. Register saves and restores
    III. Instruction fetches


    A : I only
    B : II only
    C : III only
    D : I,II and III


  •  
    .

     Correct answer is :B


  •   Question 14

    In an instruction execution pipeline, the earliest that the data TLB (Translation Lookaside Buffer) can be accessed is

    A : before effective address calculation has started
    B : during effective address calculation
    C : after effective address calculation has completed
    D : after data cache lookup has completed


  •  
    .

     Correct answer is :B


  •   Question 15

    Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache is managed using 32 bit virtual addresses and the page size is 4 Kbytes.
    double ARR[1024][1024];
    int i,j;
    /* initialize array ARR to 0.0 */
    for(i=0;i<1024;i++)
    for(j=0;j<1024;j++)
    ARR[i][j]=0.0;
    The size of double is 8Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR
    The total size of the tags in the cache directory is


    A : 32 bits
    B : 34 bits
    C : 64 bits
    D : 68 bits


  •  
    .

     Correct answer is :B


  •   Question 16

    Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache is managed using 32 bit virtual addresses and the page size is 4 Kbytes.
    double ARR[1024][1024];
    int i,j;
    /* initialize array ARR to 0.0 */
    for(i=0;i<1024;i++)
    for(j=0;j<1024;j++)
    ARR[i][j]=0.0;
    The size of double is 8Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR
    Which of the following array elements has the same cache index as ARR [0] [0]?


    A : ARR [0] [4]
    B : ARR [4] [0]
    C : ARR [0] [5]
    D : ARR [5] [0]


  •  
    .

     Correct answer is :B


  •   Question 17

    Consider a machine with a 2-way set associative data cache of size 64 Kbytes and block size 16 bytes. The cache is managed using 32 bit virtual addresses and the page size is 4 Kbytes.
    double ARR[1024][1024];
    int i,j;
    /* initialize array ARR to 0.0 */
    for(i=0;i<1024;i++)
    for(j=0;j<1024;j++)
    ARR[i][j]=0.0;
    The size of double is 8Bytes. Array ARR is located in memory starting at the beginning of virtual page 0xFF000 and stored in row major order. The cache is initially empty and no pre-fetching is done. The only data memory references made by the program are those to array ARR
    The cache hit ratio for this initialization loop is


    A : 0%
    B : 25%
    C : 50%
    D : 75%


  •  
    .

     Correct answer is :C


  •   Question 18

    Delayed branching can help in the handling of control hazards. For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false,

    A : the instruction following the conditional branch instruction in memory is executed
    B : the first instruction in the fall through path is executed
    C : the first instruction in the taken path is executed
    D : the branch takes longer to execute than any other instruction


  •  
    .

     Correct answer is :D


  •   Question 19

    Delayed branching can help in the handling of control hazards The following code is to run on a pipelined processor with one branch delay slot:
    I1: ADD R2 <- R7+R8
    I2 : SUB R4 <- R5-R6
    I3 : ADD R1 <- R2+R3
    I4 : STORE Memory [R4] <- [R1]
    BRANCH to Label if R1== 0
    Which of the instructions I1, I2, I3 or I4 can legitimately occupy the delay slot without any other program modification?


    A : I1
    B : I2
    C : I3
    D : I4


  •  
    .

     Correct answer is :D


  • MY REPORT
    TOTAL = 19
    ANSWERED =
    CORRECT / TOTAL = /19
    POSITIVE SCORE =
    NEGATIVE SCORE =
    FINAL SCORE =