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SET 4


  Question 1

A CPU generally handles an interrupt by executing an interrupt service routine

A : As soon as an interrupt is raised
B : By checking the interrupt register at the end of fetch cycle
C : By checking the interrupt register after finishing the execution of the current instruction
D : By checking the interrupt register at fixed time intervals


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     Correct answer is :C

     Solution :
      Hardware detects interrupt immediately, but CPU acts only after its current instruction. This is followed to ensure integrity of instructions.

  •   Question 2

    How many 32K x 1 RAM chips are needed to provide a memory capacity of 256K-bytes?

    A : 8
    B : 32
    C : 64
    D : 128


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     Correct answer is :C

     Solution :
      We need 256 Kbytes, i.e., 256 x 1024 x 8 bits. We have RAM chips of capacity 32 Kbits = 32 x 1024 bits. (256 * 1024 * 8)/(32 * 1024) = 64

  •   Question 3

    Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below:
    What is the number of cycles needed to execute the following loop? For (i=1 to 2) {I1; I2; I3; I4;}




    A : 16
    B : 23
    C : 28
    D : 30


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     Correct answer is :B


  •   Question 4

    A main memory unit with a capacity of 4 megabytes is built using 1M x 1-bit DRAM chips. Each DRAM chip has 1K rows of cells with 1K cells in each row. The time taken for a single refresh operation is 100 nanoseconds.The time required to perform one refresh operation on all the cells in the memory unit is

    A : 100*210 nanoseconds
    B : 100*220 nanoseconds
    C : 3200*220 nanoseconds
    D : 100 nanoseconds


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     Correct answer is :C

     Solution :
      Size of main chip = 4MB
    Size of a DRAM chip = 1M*(1/8)B
    Number of chips needed = 32
    Time for refreshing one chip = 100ns * 220

  •   Question 5

    A 5-stage pipelined processor has Instruction Fetch(IF),Instruction Decode(ID),Operand Fetch(OF),Perform Operation(PO)and Write Operand(WO)stages.The IF,ID,OF and WO stages take 1 clock cycle each for any instruction.The PO stage takes 1 clock cycle for ADD and SUB instructions,3 clock cycles for MUL instruction,and 6 clock cycles for DIV instruction respectively.Operand forwarding is used in the pipeline.What is the number of clock cycles needed to execute the following sequence of instructions



    A : 13
    B : 15
    C : 17
    D : 19


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     Correct answer is :B


  • MY REPORT
    TOTAL = 5
    ANSWERED =
    CORRECT / TOTAL = /5
    POSITIVE SCORE =
    NEGATIVE SCORE =
    FINAL SCORE =