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SET 3


  Question 1

Consider a hypothetical processor with an instruction of type LW R1, 20(R2), which during execution reads a 32-bit word from memory and stores it in a 32-bit register R1. The effective address of the memory location is obtained by the addition of constant 20 and the contents of register R2. Which of the following best reflects the addressing mode implemented by this instruction for the operand in memory?

A : Immediate Addressing
B : Register Addressing
C : Register Indirect Scaled Addressing
D : Base Indexed Addressing


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     Correct answer is :D

     Solution :
      In this problem 20 will act as base and content of R2 will be index

  •   Question 2

    A computer handles several interrupt sources of which the following are relevant for this question.
    . Interrupt from CPU temperature sensor (raises interrupt if 
      CPU temperature is too high)
    . Interrupt from Mouse(raises interrupt if the mouse is moved 
      or a button is pressed)
    . Interrupt from Keyboard(raises interrupt when a key is 
      pressed or released)
    . Interrupt from Hard Disk(raises interrupt when a disk 
      read is completed)
    Which one of these will be handled at the HIGHEST priority?


    A : Interrupt from Hard Disk
    B : Interrupt from Mouse
    C : Interrupt from Keyboard
    D : Interrupt from CPU temperature sensor


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    .

     Correct answer is :D


  •   Question 3

    Consider an instruction pipeline with four stages (S1, S2, S3 and S4) each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline registers are as given in the figure.
    What is the approximate speed up of the pipeline in steady state under ideal conditions when compared to the corresponding non-pipeline implementation?




    A : 4.0
    B : 2.5
    C : 1.1
    D : 3.0


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     Correct answer is :B

     Solution :
      (5+6+11+8)/(11+1) = 30/12 = 2.5 answer

  •   Question 4

    An 8KB direct mapped write-back cache is organized as multiple blocks, each of size 32-bytes. The processor generates 32-bit addresses. The cache controller maintains the tag information for each cache block comprising of the following. 1 Valid bit 1 Modified bit As many bits as the minimum needed to identify the memory block mapped in the cache. What is the total size of memory needed at the cache controller to store metadata (tags) for the cache?

    A : 4864 bits
    B : 6144 bits
    C : 6656 bits
    D : 5376 bits


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     Correct answer is :D

     Solution :
      We have
    tag = 19 bits, index = 8bits and offset = 5 bits + there are 2 extra bits so total 21 bits for meta data.
    21*256 ( as all the blocks will have 21 bits metadata)

  •   Question 5

    On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 5000 bytes from an I/O device to memory.
                  Initialize the address register
                  Initialize the count to 500
            LOOP: Load a byte from device
                  Store in memory at address given by address register
                  Increment the address register
                  Decrement the count
                  If count != 0 go to LOOP 
    

    Assume that each statement in this program is equivalent to machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute. The designer of the system also has an alternate approach of using DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory. What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?


    A : 3.4
    B : 4.4
    C : 5.1
    D : 6.7


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     Correct answer is :A

     Solution :
      No. of clock cycles required by using load-store approach = 2 + 500 × 7 = 3502 and that of by using DMA = 20 + 500 × 2 = 1020 Required speed up= 3502/1020 = 3.4

  •   Question 6

    Consider evaluating the following expression tree on a machine with load-store architecture in which memory can be accessed only through load and store instructions. The variables a, b, c, d and e are initially stored in memory. The binary operators used in this expression tree can be evaluated by the machine only when the operands are in registers. The instructions produce result only in a register. If no intermediate results can be stored in memory, what is the minimum number of registers needed to evaluate this expression?



    A : 2
    B : 9
    C : 5
    D : 3


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    .

     Correct answer is :D


  •   Question 7

    Register renaming is done is pipelined processors

    A : as an alternative to register allocation at compile time
    B : for efficient access to function parameters and local variables
    C : to handle certain kinds of hazards
    D : as part of address translation


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     Correct answer is :C

     Solution :
      Register renaming is done to eliminate WAR/WAW hazards.

  •   Question 8

    The amount of ROM needed to implement a 4 bit multiplier is

    A : 64 bits
    B : 128 bits
    C : 1 Kbits
    D : 2 Kbits


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     Correct answer is :D

     Solution :
      For a 4 bit multiplier there are 24 * 24 = 256 combinations.
    Output will contain 8 bits.
    So the amount of ROM needed is 8*28 bits = 2Kbits.

  •   Question 9

    A RAM chip has a capacity of 1024 words of 8 bits each (1K×8) . The number of 2× 4 decoders with enable line needed to construct a 16K×16 RAM from1K×8 RAM is

    A : 4
    B : 5
    C : 6
    D : 7


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     Correct answer is :B

     Solution :
      RAM chip size = 1k ×8[1024 words of 8 bits each] RAM to construct =16k ×16
    Number of chips required = 16k*16/1k*8 = 16*2 [16 chips vertically with each having 2 chips horizontally]
    So to select one chip out of 16 vertical chips, we need 4 x 16 decoder.
    Available decoder is – 2 x 4 decoder
    To be constructed is 4 x 16 decoder
    So we need 5, 2 x 4 decoder in total to construct 4 x 16 decoder.


  •   Question 10

    Consider an instruction pipeline with five stages without any branch prediction: Fetch Instruction (FI), Decode Instruction (DI), Fetch Operand (FO), Execute Instruction (EI) and Write Operand (WO). The stage delays for FI, DI, FO, EI and WO are 5 ns, 7 ns, 10 ns, 8 ns and 6 ns, respectively. There are intermediate storage buffers after each stage and the delay of each buffer is 1 ns. A program consisting of 12 instructions I1,I2,I3.........I12 is executed in this pipelined processor. Instruction 4 I is the only branch instruction and its branch target is 9 I . If the branch is taken during the execution of this program, the time (in ns) needed to complete the program is

    A : 132
    B : 165
    C : 176
    D : 328


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     Correct answer is :B

     Solution :
      Clock period=Maximum stage delay+ overhead (Buffer) =10+1=11 ns
    Assume FI-1, DI-2, FO-3, EI-4, WO-5
    I1 : 1 2 3 4 5
    I2 : - 1 2 3 4 5
    I3 : - - 1 2 3 4 5
    I4 : - - - 1 2 3 4 5
    I5 : - - - - 1 2 3 4 5
    I6 : - - - - - 1 2 3 4 5
    I7 : - - - - - - 1 2 3 4 5
    I8 : - - - - - - - 1 2 3 4 5
    I9 : - - - - - - - - 1 2 3 4 5
    I10 : - - - - - - - - - 1 2 3 4 5
    I11 : - - - - - - - - - - 1 2 3 4 5
    I12 : - - - - - - - - - - - 1 2 3 4 5
    So number of clocks required to complete the program is = 15 clocks and time taken is = 15 ×11 ns=165 ns.

  •   Question 11

    Consider the following sequence of micro–operations
    MBR <- PC
    MAR <- X
    PC <- Y
    Memory <- MBR
    Which one of the following is a possible operation performed by this sequence?


    A : Instruction fetch
    B : Operand fetch
    C : Conditional branch
    D : Initiation of interrupt service


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     Correct answer is :D

     Solution :
      PC content is stored in memory via MBR and PC gets new address from Y. It represents a function call (routine), which is matching with interrupt service initiation

  • MY REPORT
    TOTAL = 11
    ANSWERED =
    CORRECT / TOTAL = /11
    POSITIVE SCORE =
    NEGATIVE SCORE =
    FINAL SCORE =