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SET 1


  Question 1

For computers based on three-address instruction formats, each address field can be used to specify which of the following:
S1: A memory operand
S2: A processor register
S3: An implied accumulator register


A : Either S1 or S2
B : Either S2 or S3
C : Only S2 or S3
D : All of S1 ,S2 and S3


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     Correct answer is :A


  •   Question 2

    Consider a non-pipelined processor with a clock rate of 2.5 gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, the clock speed is reduced to 2 gigahertz. Assume that there are no stalls in the pipeline. The speed up achieved in this pipelined processor is __________.



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     Correct answer is :3.2


  •   Question 3

    The least number of temporary variables required to create a three-address code in static single assignment form for the expression q + r/3 + s t * 5 + u * v/w is _________.



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     Correct answer is :3


  •   Question 4

    Assume that for a certain processor, a read request takes 50 nanoseconds on a cache miss and 5 nanoseconds on a cache hit. Suppose while running a program, it was observed that 80% of the processors read requests result in a cache hit. The average and access time in nanoseconds is _______.



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     Correct answer is :14

     Solution :
      Average read access time =[(0.8)(5)+(0.2)(50)] ns.
    =4+10 =14ns

  •   Question 5

    Consider a processor with byte-addressable memory. Assume that all registers, including Program Counter (PC) and Program Status Word (PSW), are of size 2 bytes. A stack in the main memory is implemented from memory location (0100) 16 and it grows upward. The stack pointer (SP) points to the top element of the stack. The current value of SP is (016E)16. The CALL instruction is of two words, the first word is the op-code and the second word is the starting address of the subroutine. ( oneword = 2bytes) . The CALL instruction is implemented as follows:
    Store the current Vale of PC in the Stack
    Store the value of PSW register in the stack
    Load the starting address of the subroutine in PC
    The content of PC just before the fetch of a CALL instruction is (5FA0)16. After execution of the CALL instruction, the value of the stack pointer is


    A : (016A)16
    B : (016C)16
    C : (0170)16
    D : (0172)16


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     Correct answer is :D


  •   Question 6

    Consider the sequence of machine instruction given below:
    MUL R5,R0,R1
    DIV R6,R2,R3
    ADD R7,R5,R6
    SUB R8,R7,R4
    In the above sequence, R0 to R8 are general purpose registers. In the instructions shown. the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages (1) Instruction Fetch and Decode (IF), (2) Operand Fetch (OF), (3) Perform Operation (PO) and (4) Write back the result (WB) . The IF,OF and WB stages take 1 clock cycle each for any instruction The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is __________




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     Correct answer is :13

     Solution :
      I=> Instruction fetch
    O=>Operand Fetch
    P=>Perform operation
    W = >write back the result


  •   Question 7

    Consider a machine with byte addressable main memory of 2020 bytes, block size of 16 bytes and a direct mapped cache having 212 cache lines. Let the address of two consecutive bytes in main memory be (E201F)16 and (E2020)16 . What are the tag and cache line address (in hex) for main memory address (E201F)16?

    A : E,201
    B : F,201
    C : E,E20
    D : 2,01F


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     Correct answer is :A


  •   Question 8

    Consider the following reservation table for a pipeline having three stages S1, S2, and S3.
    The minimum average latency (MAL) is ________.






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     Correct answer is :*


  •   Question 9

    Consider the following code sequence having five instructions I1 to I5. Each of these instructions has the following format.
    OP Ri, Rj, Rk
    Where operation OP is performed on contents of registers Rj and Rk and the results is stored in register Ri.
    I1 :ADD R1, R2, R3
    I2:MUL R7, R1, R3
    I3 :SUB R4, R1, R5
    I4 :ADD R3, R 2, R 4
    I5 :MUL R7,R8, R9
    Consider the following three statements.
    S1: There is an anti-dependence between instructions I2 and I5
    S2: There is an anti-dependence between instructions I2 and I4
    S3: Within an instruction pipeline an anti-dependence always creates on or more stalls
    Which one of above stamens is/are correct?


    A : Only S1 is true
    B : Only S2 is true
    C : Only S1 and S3 are true
    D : Only S2 and S3 are true


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     Correct answer is :D


  • MY REPORT
    TOTAL = 9
    ANSWERED =
    CORRECT / TOTAL = /9
    POSITIVE SCORE =
    NEGATIVE SCORE =
    FINAL SCORE =